Today's high performance microprocessors must have the capability of supporting fast floating point and integer calculations. In order to support various applications environments (i.e. graphics image rendering) these microprocessors must perform multiply operations, using operands that have a 32 or 64-bit word length, at high clock rates. Typically, these microprocessors rely upon multiplier arrays to perform a set of floating point, integer and graphic multiply instructions. Generally, the number of circuit elements in a multiplier is proportional to N.sup.2 (where N is the word length in bits). Thus, one critical factor affecting implementation of a multiplier is the global layout considerations ("floorplan") of the circuit elements. Another critical factor is the speed at which the multiplier performs the multiply operation.
Since tree multipliers have a delay proportional to log(N), they are preferable in terms of performance to array multipliers, whose delay is proportional to N. Tree multipliers require large shifts of data perpendicular to the data path, therefore, implementation of tree multipliers is routing intensive. Thus, even though tree multipliers offer speed advantages over array multipliers, microprocessor designers have traditionally avoided using tree multipliers due to the circuit area required for their implementation.
It is, therefore, desirable to provide a tree multiplier floorplan which reduces the circuit area required for its implementation, while still providing the capability to perform high speed calculations.